|
capnproto
|
public |
An insanely fast data interchange format and capability-based RPC system.
|
2025-03-25 |
|
capnproto-java
|
public |
Cap'n Proto in pure Java
|
2025-03-25 |
|
symbiflow-vtr-gui
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
|
symbiflow-vtr
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
|
verilator-uhdm
|
public |
No Summary
|
2025-03-25 |
|
uhdm-integration-verilator
|
public |
No Summary
|
2025-03-25 |
|
surelog-uhdm
|
public |
No Summary
|
2025-03-25 |
|
prjxray-db
|
public |
Project X-Ray Database: XC7 Series.
|
2025-03-25 |
|
prjxray-tools
|
public |
Documenting the Xilinx 7-series bit-stream format.
|
2025-03-25 |
|
vtr-no-gui
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
|
nextpnr-ice40
|
public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
|
2025-03-25 |
|
prjxray
|
public |
Documenting the Xilinx 7-series bit-stream format.
|
2025-03-25 |
|
symbiflow-toolchain-xray
|
public |
Conda metapackage combining VtR, Yosys and Yosys plugins.
|
2025-03-25 |
|
nextpnr-xilinx
|
public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
|
2025-03-25 |
|
surelog
|
public |
Parser/Compiler for SystemVerilog
|
2025-03-25 |
|
verible
|
public |
The main mission is to parse SystemVerilog (IEEE 1800-2017) for a wide variety of applications.
|
2025-03-25 |
|
sv-parser
|
public |
SystemVerilog parser library fully complient with IEEE 1800-2017
|
2025-03-25 |
|
moore
|
public |
HDL compiler based on LLHD
|
2025-03-25 |
|
slang
|
public |
Parser and compiler library for SystemVerilog
|
2025-03-25 |
|
libxml2
|
public |
The XML C parser and toolkit of Gnome
|
2025-03-25 |
|
netlistsvg
|
public |
netlistsvg draws an SVG schematic from a yosys JSON netlist.
|
2025-03-25 |
|
tree-sitter-verilog
|
public |
Verilog grammar for tree-sitter
|
2025-03-25 |
|
sigrok-cli
|
public |
The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types (e.g. logic analyzers, oscilloscopes, and many more).
|
2025-03-25 |
|
odin_ii
|
public |
Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
|
2025-03-25 |
|
zachjs-sv2v
|
public |
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
|
2025-03-25 |
