capnproto
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public |
An insanely fast data interchange format and capability-based RPC system.
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2025-03-25 |
capnproto-java
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public |
Cap'n Proto in pure Java
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2025-03-25 |
symbiflow-vtr-gui
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2025-03-25 |
symbiflow-vtr
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2025-03-25 |
verilator-uhdm
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public |
No Summary
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2025-03-25 |
uhdm-integration-verilator
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public |
No Summary
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2025-03-25 |
surelog-uhdm
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public |
No Summary
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2025-03-25 |
prjxray-db
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public |
Project X-Ray Database: XC7 Series.
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2025-03-25 |
prjxray-tools
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public |
Documenting the Xilinx 7-series bit-stream format.
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2025-03-25 |
vtr-no-gui
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
nextpnr-ice40
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2025-03-25 |
prjxray
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public |
Documenting the Xilinx 7-series bit-stream format.
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2025-03-25 |
symbiflow-toolchain-xray
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public |
Conda metapackage combining VtR, Yosys and Yosys plugins.
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2025-03-25 |
nextpnr-xilinx
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
|
2025-03-25 |
surelog
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public |
Parser/Compiler for SystemVerilog
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2025-03-25 |
verible
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public |
The main mission is to parse SystemVerilog (IEEE 1800-2017) for a wide variety of applications.
|
2025-03-25 |
sv-parser
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public |
SystemVerilog parser library fully complient with IEEE 1800-2017
|
2025-03-25 |
moore
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public |
HDL compiler based on LLHD
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2025-03-25 |
slang
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public |
Parser and compiler library for SystemVerilog
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2025-03-25 |
libxml2
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public |
The XML C parser and toolkit of Gnome
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2025-03-25 |
netlistsvg
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public |
netlistsvg draws an SVG schematic from a yosys JSON netlist.
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2025-03-25 |
tree-sitter-verilog
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public |
Verilog grammar for tree-sitter
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2025-03-25 |
sigrok-cli
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public |
The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types (e.g. logic analyzers, oscilloscopes, and many more).
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2025-03-25 |
odin_ii
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public |
Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
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2025-03-25 |
zachjs-sv2v
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public |
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
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2025-03-25 |