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surelog
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public |
Parser/Compiler for SystemVerilog
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2023-06-16 |
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verible
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public |
The main mission is to parse SystemVerilog (IEEE 1800-2017) for a wide variety of applications.
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2023-06-16 |
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moore
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public |
HDL compiler based on LLHD
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2023-06-16 |
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sv-parser
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public |
SystemVerilog parser library fully complient with IEEE 1800-2017
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2023-06-16 |
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slang
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public |
Parser and compiler library for SystemVerilog
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2023-06-16 |
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netlistsvg
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public |
netlistsvg draws an SVG schematic from a yosys JSON netlist.
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2023-06-16 |
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tree-sitter-verilog
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public |
Verilog grammar for tree-sitter
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2023-06-16 |
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odin_ii
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public |
Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
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2023-06-16 |
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zachjs-sv2v
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public |
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
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2023-06-16 |
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vtr
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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icestorm
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public |
Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
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2023-06-16 |
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iverilog
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public |
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format.
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2023-06-16 |
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arachne-pnr
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public |
Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device. Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2023-06-16 |
