| arachne-pnr | v0.0 | Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device. Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. | Mar 25, 2025 | — |
| binutils-riscv32-elf | 2.28.0 | A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. | Mar 25, 2025 | GPL |
| capnproto | 0.8.0 | An insanely fast data interchange format and capability-based RPC system. | Mar 25, 2025 | MIT |
| capnproto-java | 0.1.5_0009_gb60bc1e | Cap'n Proto in pure Java | Mar 25, 2025 | MIT |
| icestorm | 0.0_0771_gda52117 | Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. | Mar 25, 2025 | — |
| iverilog | 10.0.0_0869_g359b2b65 | Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format. | Mar 25, 2025 | GPLv2 |
| libusb | 1.0.22 | A cross-platform library to access USB devices | Mar 25, 2025 | LGPLv2.1 |
| libxml2 | 2.9.10 | The XML C parser and toolkit of Gnome | Mar 25, 2025 | MIT |
| moore | 0.11.0_0035_g386fa01 | HDL compiler based on LLHD | Mar 25, 2025 | MIT |
| netlistsvg | 1.0.2_0000_geb9dc54 | netlistsvg draws an SVG schematic from a yosys JSON netlist. | Mar 25, 2025 | MIT |
| nextpnr | 0.0_2604_gf44498a | nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. | Mar 25, 2025 | ISC |
| nextpnr-ice40 | 0.0_2862_gc6cdf305 | nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. | Mar 25, 2025 | ISC |
| nextpnr-xilinx | 0.0_2814_gd40ffba7 | nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. | Mar 25, 2025 | ISC |
| odin_ii | 8.0.0.rc1_1526_ge6de331da | Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist. | Mar 25, 2025 | MIT |
| openocd | 0.10.0_1423_g3ffa14b04 | OpenOCD provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support | Mar 25, 2025 | GPLv2+ |
| prjxray | 0.1_2557_ge81bd909 | Documenting the Xilinx 7-series bit-stream format. | Mar 25, 2025 | ISC |
| prjxray-db | 0.0_0239_gd87c844 | Project X-Ray Database: XC7 Series. | Mar 25, 2025 | CC0-1.0 |
| prjxray-tools | 0.1_2726_g77e8b24c | Documenting the Xilinx 7-series bit-stream format. | Mar 25, 2025 | ISC |
| sigrok-cli | 0.6.0_0085_g0171a4a | The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types (e.g. logic analyzers, oscilloscopes, and many more). | Mar 25, 2025 | GPLv3 |
| slang | 0.5_0180_g407a4fad | Parser and compiler library for SystemVerilog | Mar 25, 2025 | MIT |
| surelog | 0.0_1936_gafbcef84 | Parser/Compiler for SystemVerilog | Mar 25, 2025 | Apache |
| surelog-uhdm | 0.0_0151_gd4c942a | — | Mar 25, 2025 | — |
| sv-parser | 0.10.0_0001_gb1c3f41 | SystemVerilog parser library fully complient with IEEE 1800-2017 | Mar 25, 2025 | MIT |
| symbiflow-toolchain-xray | 0.0_0717_gb5801b7 | Conda metapackage combining VtR, Yosys and Yosys plugins. | Mar 25, 2025 | — |
| symbiflow-vtr | 8.0.0.rc2_5378_g45ed3911e | The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. | Mar 25, 2025 | MIT |
