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surelog
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public |
Parser/Compiler for SystemVerilog
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2025-03-25 |
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odin_ii
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public |
Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
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2025-03-25 |
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sv-parser
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public |
SystemVerilog parser library fully complient with IEEE 1800-2017
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2025-03-25 |
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slang
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public |
Parser and compiler library for SystemVerilog
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2025-03-25 |
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netlistsvg
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public |
netlistsvg draws an SVG schematic from a yosys JSON netlist.
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2025-03-25 |
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moore
|
public |
HDL compiler based on LLHD
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2025-03-25 |
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verible
|
public |
The main mission is to parse SystemVerilog (IEEE 1800-2017) for a wide variety of applications.
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2025-03-25 |
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tree-sitter-verilog
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public |
Verilog grammar for tree-sitter
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2025-03-25 |
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netgen
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public |
Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.
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2025-03-25 |
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vtr-optimized
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2025-03-25 |
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dummy-pkg
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public |
No Summary
|
2025-03-25 |
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zachjs-sv2v
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public |
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
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2025-03-25 |
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nextpnr-xilinx
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2025-03-25 |
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quicklogic-vtr
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public |
A metapackage installing upstream version of the Verilog-to-Routing (VTR).
|
2025-03-25 |
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quicklogic-vtr-gui
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public |
A metapackage installing upstream version of the Verilog-to-Routing (VTR) with GUI support.
|
2025-03-25 |
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quicklogic-yosys-plugins
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public |
No Summary
|
2025-03-25 |
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quicklogic-yosys
|
public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2025-03-25 |
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symbiflow-yosys-plugins
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public |
No Summary
|
2025-03-25 |
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capnproto-java
|
public |
Cap'n Proto in pure Java
|
2025-03-25 |
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capnproto
|
public |
An insanely fast data interchange format and capability-based RPC system.
|
2025-03-25 |
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prjxray-tools
|
public |
Documenting the Xilinx 7-series bit-stream format.
|
2025-03-25 |
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prjxray-db
|
public |
Project X-Ray Database: XC7 Series.
|
2025-03-25 |
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symbiflow-vtr
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
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vtr-gui
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
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xilinx-vivado
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public |
Conda metapackage for Xilinx Vivado SDK. Package checks only Vivado version.
|
2025-03-25 |
