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verilator-uhdm
|
public |
No Summary
|
2025-03-25 |
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symbiflow-yosys-plugins
|
public |
No Summary
|
2025-03-25 |
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antmicro-yosys-complete
|
public |
Conda metapackage combining Antmicro Yosys fork and Yosys plugins.
|
2025-03-25 |
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symbiflow-yosys
|
public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2025-03-25 |
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antmicro-yosys-plugins
|
public |
No Summary
|
2025-03-25 |
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antmicro-yosys
|
public |
No Summary
|
2025-03-25 |
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quicklogic-vtr-gui
|
public |
A metapackage installing upstream version of the Verilog-to-Routing (VTR) with GUI support.
|
2025-03-25 |
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surelog
|
public |
Parser/Compiler for SystemVerilog
|
2025-03-25 |
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surelog-uhdm
|
public |
No Summary
|
2025-03-25 |
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quicklogic-vtr
|
public |
A metapackage installing upstream version of the Verilog-to-Routing (VTR).
|
2025-03-25 |
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vtr-optimized
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
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sv-parser
|
public |
SystemVerilog parser library fully complient with IEEE 1800-2017
|
2025-03-25 |
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odin_ii
|
public |
Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
|
2025-03-25 |
|
vtr-gui
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
|
slang
|
public |
Parser and compiler library for SystemVerilog
|
2025-03-25 |
|
moore
|
public |
HDL compiler based on LLHD
|
2025-03-25 |
|
verible
|
public |
The main mission is to parse SystemVerilog (IEEE 1800-2017) for a wide variety of applications.
|
2025-03-25 |
|
symbiflow-vtr-gui
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
|
vtr
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
|
symbiflow-vtr
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
|
yosys
|
public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2025-03-25 |
|
quicklogic-yosys
|
public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2025-03-25 |
|
verilator
|
public |
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators.
|
2025-03-25 |
|
xilinx-vivado
|
public |
Conda metapackage for Xilinx Vivado SDK. Package checks only Vivado version.
|
2025-03-25 |
|
iverilog
|
public |
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format.
|
2025-03-25 |
