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Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Info: This package contains files in non-standard
labels.
linux-64
v0.9_0_g40d9e120
osx-64
v0.9_0_g40d9e120
conda install
To install this package run one of the following: conda install antmicro::symbiflow-yosysconda install antmicro/label/ci-master-1154556000::symbiflow-yosys
