symbiflow-yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
2 items
| Name | Latest Version |
|---|
ci-master-1154556000 | 0.9_2_gb7d46be4 |
main | 0.9_0_g40d9e120 |