yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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Summary
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Information Last Updated
Mar 25, 2025 at 16:23
License
ISC
Total Downloads
60
Platforms
Linux 64 Version: 0.9_5253_gdcd9f0af
macOS 64 Version: 0.9_5253_gdcd9f0af
Win 64 Version: 0.9_5253_gdcd9f0af