yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Installation
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About
Summary
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Last Updated
Feb 25, 2021 at 14:17
License
ISC
Total Downloads
60
Supported Platforms
linux-64
macOS-64
win-64