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sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.

Type	Size	Name	Uploaded	Downloads	Labels
conda	1.1 MB	\| linux-64/zachjs-sv2v-0.0.5_0021_g6d907e0-20200924_170135.tar.bz2	4 years and 13 days ago	26	main
conda	1.1 MB	\| linux-64/zachjs-sv2v-0.0.5_0021_g6d907e0-20200923_144930.tar.bz2	4 years and 14 days ago	2	main
conda	1.1 MB	\| linux-64/zachjs-sv2v-0.0.5_0021_g6d907e0-20200921_133616.tar.bz2	4 years and 17 days ago	5	main
conda	1.1 MB	\| linux-64/zachjs-sv2v-0.0.5_0021_g6d907e0-20200916_091654.tar.bz2	4 years and 22 days ago	28	main
conda	1.1 MB	\| linux-64/zachjs-sv2v-0.0.5_0021_g6d907e0-20200916_072439.tar.bz2	4 years and 22 days ago	1	main

SymbiFlow / packages / zachjs-sv2v

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