| Package Name | Access | Summary | Updated |
|---|---|---|---|
| xls | public | Accelerated HW Synthesis | 2024-06-27 |
| yosys | public | Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. | 2024-02-23 |
| surelog | public | Parser/Compiler for SystemVerilog | 2024-02-23 |
