Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
conda install litex-hub::yosysconda install litex-hub/label/ci-master-1188059080::yosysconda install litex-hub/label/ci-master-1613391290::yosysconda install litex-hub/label/ci-master-1925127487::yosysconda install litex-hub/label/ci-master-2229869394::yosysconda install litex-hub/label/ci-master-939595724::yosys