prjtrellis
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
Installation
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Usage Tracking
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About
Summary
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
Last Updated
Jan 8, 2020 at 07:54
License
ISC
Total Downloads
137
Supported Platforms
linux-64