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nextpnr-xilinx
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2025-03-25 |
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nextpnr-ecp5
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2025-03-25 |
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uhdm-integration-yosys
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public |
No Summary
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2025-03-25 |
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nextpnr-ice40
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2025-03-25 |
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yosys-uhdm
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public |
No Summary
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2025-03-25 |
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uhdm-integration-verilator
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public |
No Summary
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2025-03-25 |
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nextpnr-generic
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2025-03-25 |
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arachne-pnr
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public |
Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device. Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2025-03-25 |
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verilator-uhdm
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public |
No Summary
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2025-03-25 |
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symbiflow-yosys-plugins
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public |
No Summary
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2025-03-25 |
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antmicro-yosys-complete
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public |
Conda metapackage combining Antmicro Yosys fork and Yosys plugins.
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2025-03-25 |
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symbiflow-yosys
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public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2025-03-25 |
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antmicro-yosys-plugins
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public |
No Summary
|
2025-03-25 |
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antmicro-yosys
|
public |
No Summary
|
2025-03-25 |
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quicklogic-vtr-gui
|
public |
A metapackage installing upstream version of the Verilog-to-Routing (VTR) with GUI support.
|
2025-03-25 |
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surelog
|
public |
Parser/Compiler for SystemVerilog
|
2025-03-25 |
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surelog-uhdm
|
public |
No Summary
|
2025-03-25 |
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quicklogic-vtr
|
public |
A metapackage installing upstream version of the Verilog-to-Routing (VTR).
|
2025-03-25 |
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vtr-optimized
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
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sv-parser
|
public |
SystemVerilog parser library fully complient with IEEE 1800-2017
|
2025-03-25 |
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odin_ii
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public |
Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
|
2025-03-25 |
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vtr-gui
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2025-03-25 |
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slang
|
public |
Parser and compiler library for SystemVerilog
|
2025-03-25 |
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moore
|
public |
HDL compiler based on LLHD
|
2025-03-25 |
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verible
|
public |
The main mission is to parse SystemVerilog (IEEE 1800-2017) for a wide variety of applications.
|
2025-03-25 |
