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nextpnr-ecp5
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2023-06-16 |
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nextpnr-ice40
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2023-06-16 |
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arachne-pnr
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public |
Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device. Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2023-06-16 |
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symbiflow-yosys
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public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2023-06-16 |
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antmicro-yosys
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public |
No Summary
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2023-06-16 |
