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prjoxide
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public |
Documenting Lattice 28nm FPGA parts
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2023-06-16 |
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yosys-uhdm
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public |
No Summary
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2023-06-16 |
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vtr-optimized
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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sv-parser
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public |
SystemVerilog parser library fully complient with IEEE 1800-2017
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2023-06-16 |
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vtr-gui
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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vtr
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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symbiflow-vtr
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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quicklogic-yosys
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public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2023-06-16 |
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xilinx-vivado
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public |
Conda metapackage for Xilinx Vivado SDK. Package checks only Vivado version.
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2023-06-16 |
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iverilog
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public |
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format.
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2023-06-16 |
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prjtrellis
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public |
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
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2023-06-16 |
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prjxray-db
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public |
Project X-Ray Database: XC7 Series.
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2023-06-16 |
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icestorm
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public |
Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
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2023-06-16 |
