prjtrellis
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
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1.0_176_gf93243b
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Summary
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
Last Updated
Feb 25, 2021 at 14:01
License
ISC
Total Downloads
113
Supported Platforms
linux-64
macOS-64
win-64