| Package Name | Access | Summary | Updated |
|---|---|---|---|
| prjoxide | public | Documenting Lattice 28nm FPGA parts | 2025-03-25 |
| yosys-uhdm | public | No Summary | 2025-03-25 |
| vtr-optimized | public | The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. | 2025-03-25 |
| sv-parser | public | SystemVerilog parser library fully complient with IEEE 1800-2017 | 2025-03-25 |
| vtr-gui | public | The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. | 2025-03-25 |
| vtr | public | The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. | 2025-03-25 |
| symbiflow-vtr | public | The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. | 2025-03-25 |
| quicklogic-yosys | public | Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. | 2025-03-25 |
| xilinx-vivado | public | Conda metapackage for Xilinx Vivado SDK. Package checks only Vivado version. | 2025-03-25 |
| iverilog | public | Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format. | 2025-03-25 |
| prjtrellis | public | Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation. | 2025-03-25 |
| prjxray-db | public | Project X-Ray Database: XC7 Series. | 2025-03-25 |
| icestorm | public | Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. | 2025-03-25 |
