The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
| Label | Latest Version |
|---|---|
| main | 7.0.5_7049_g125359595 |
| old | v8.0.0_rc1_1082_g2b412e99b_0000_g2b412e99b |
