The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
| Label | Latest Version |
|---|---|
| main | 8.0.0.rc2_3575_g253f75b6d |
