yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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Summary
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Last Updated
Jan 15, 2020 at 08:53
License
ISC
Total Downloads
118.4K
Supported Platforms
linux-64