zachjs-sv2v
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
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0.0.8_27_g40f66e0
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About
Summary
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
Last Updated
Apr 8, 2021 at 05:35
License
BSD
Total Downloads
24
Supported Platforms
linux-64