quicklogic-yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
2 items
| Name | Latest Version |
|---|
ci-master-1164514854 | 0.8.0_105_gd282be04 |
main | 0.8.0_93_gb2a09da0 |