The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
| Label | Latest Version |
|---|---|
| main | 8.0.0_3347_g7be7cbe3d |
| ci-master-1164514854 | 8.0.0_4137_g1a00ea97a |
