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antmicro / packages / symbiflow-yosys

Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Label Latest Version
main 0.9_0_g40d9e120
ci-master-1154556000 0.9_2_gb7d46be4

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