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symbiflow-vtr-gui
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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vtr
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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symbiflow-vtr
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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yosys
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public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2023-06-16 |
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quicklogic-yosys
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public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2023-06-16 |
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verilator
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public |
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators.
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2023-06-16 |
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xilinx-vivado
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public |
Conda metapackage for Xilinx Vivado SDK. Package checks only Vivado version.
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2023-06-16 |
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iverilog
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public |
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format.
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2023-06-16 |
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quicklogic-yosys-plugins
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public |
No Summary
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2023-06-16 |
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prjtrellis
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public |
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
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2023-06-16 |
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magic
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public |
Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.
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2023-06-16 |
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prjxray-tools
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public |
Documenting the Xilinx 7-series bit-stream format.
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2023-06-16 |
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prjxray-db
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public |
Project X-Ray Database: XC7 Series.
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2023-06-16 |
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icestorm
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public |
Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
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2023-06-16 |
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sigrok-cli
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public |
The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types (e.g. logic analyzers, oscilloscopes, and many more).
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2023-06-16 |
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zachjs-sv2v
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public |
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
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2023-06-16 |
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netlistsvg
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public |
netlistsvg draws an SVG schematic from a yosys JSON netlist.
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2023-06-16 |
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netgen
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public |
Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.
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2023-06-16 |
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renode
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public |
No Summary
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2023-06-16 |
