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libusb
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public |
A cross-platform library to access USB devices
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2025-03-25 |
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nextpnr
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2025-03-25 |
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verilator
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public |
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators.
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2025-03-25 |
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openocd
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public |
OpenOCD provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support
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2025-03-25 |
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binutils-riscv32-elf
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public |
A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code.
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2025-03-25 |
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arachne-pnr
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public |
Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device. Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2025-03-25 |
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vtr
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public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2025-03-25 |
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icestorm
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public |
Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
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2025-03-25 |
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iverilog
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public |
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format.
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2025-03-25 |
