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klayout
|
public |
Your Mask Layout Friend
|
2024-07-18 |
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nextpnr-ecp5
|
public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
|
2024-07-18 |
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nextpnr-ice40
|
public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
|
2024-07-18 |
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nextpnr-nexus
|
public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
|
2024-07-18 |
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gperftools
|
public |
No Summary
|
2024-07-18 |
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verilator
|
public |
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators.
|
2024-07-18 |
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nextpnr-fpga_interchange
|
public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
|
2024-07-18 |
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nextpnr-generic
|
public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
|
2024-07-18 |
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prjxray-tools
|
public |
Documenting the Xilinx 7-series bit-stream format.
|
2024-07-18 |
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xschem
|
public |
Schematic capture and netlisting EDA tool.
|
2024-07-18 |
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magic
|
public |
Magic VLSI Layout Tool
|
2024-07-18 |
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tcllib
|
public |
Tcllib is a collection of utility modules for Tcl.
|
2024-07-18 |
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netgen
|
public |
Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.
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2024-07-18 |
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verible
|
public |
The main mission is to parse SystemVerilog (IEEE 1800-2017) for a wide variety of applications.
|
2024-07-17 |
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xls
|
public |
Accelerated HW Synthesis
|
2024-06-27 |
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xilinx-vivado
|
public |
Conda metapackage for Xilinx Vivado SDK. Package checks only Vivado version.
|
2024-06-22 |
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ngspice
|
public |
The open source spice simulator for electric and electronic circuit.
|
2024-06-21 |
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tree-sitter-verilog
|
public |
Verilog grammar for tree-sitter
|
2024-05-12 |
|
sv-parser
|
public |
SystemVerilog parser library fully complient with IEEE 1800-2017
|
2024-04-21 |
|
icestorm
|
public |
Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
|
2024-04-03 |
|
prjtrellis
|
public |
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
|
2024-03-31 |
|
open_pdks.sky130a
|
public |
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.
|
2024-03-21 |
|
open_pdks.gf180mcuc
|
public |
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/GlobalFoundries 180nm process.
|
2024-03-20 |
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zachjs-sv2v
|
public |
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
|
2024-03-12 |
|
openroad
|
public |
OpenROAD is an unified application implementing an RTL-to-GDS Flow.
|
2024-03-03 |
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verilator-uhdm
|
public |
No Summary
|
2024-03-01 |
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yosys
|
public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2024-02-23 |
|
surelog-uhdm
|
public |
No Summary
|
2024-02-23 |
|
surelog
|
public |
Parser/Compiler for SystemVerilog
|
2024-02-23 |
|
prjxray-db
|
public |
Project X-Ray Database: XC7 Series.
|
2024-02-23 |
|
prjoxide
|
public |
Documenting Lattice 28nm FPGA parts
|
2024-02-23 |
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libunwind
|
public |
No Summary
|
2024-02-23 |
|
iverilog
|
public |
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool.
It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.
For batch simulation, the compiler can generate an intermediate form called vvp assembly.
This intermediate form is executed by the ``vvp'' command.
For synthesis, the compiler generates netlists in the desired format.'
|
2024-02-17 |
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openlane
|
public |
OpenLane is an automated RTL to GDSII flow.
|
2023-11-04 |
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yosys-uhdm
|
public |
No Summary
|
2023-08-31 |
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yosys-symbiflow-plugins
|
public |
No Summary
|
2023-06-23 |
|
symbiflow-yosys-plugins
|
public |
No Summary
|
2023-06-23 |
|
openfpgaloader
|
public |
Universal utility for programming FPGAs.
|
2023-06-16 |
|
libhidapi
|
public |
Multi-platform library which allows interfacing with USB and Bluetooth HID-Class devices
|
2023-06-16 |
|
antmicro-yosys-complete
|
public |
Conda metapackage combining Antmicro Yosys fork and Yosys plugins.
|
2023-06-16 |
|
antmicro-yosys-plugins
|
public |
No Summary
|
2023-06-16 |
|
antmicro-yosys
|
public |
No Summary
|
2023-06-16 |
|
uhdm-integration-yosys
|
public |
No Summary
|
2023-06-16 |
|
uhdm-integration-verilator
|
public |
No Summary
|
2023-06-16 |
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odin_ii
|
public |
Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
|
2023-06-16 |
|
slang
|
public |
Parser and compiler library for SystemVerilog
|
2023-06-16 |
|
netlistsvg
|
public |
netlistsvg draws an SVG schematic from a yosys JSON netlist.
|
2023-06-16 |
|
moore
|
public |
HDL compiler based on LLHD
|
2023-06-16 |
|
vtr-optimized
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2023-06-16 |
|
dummy-pkg
|
public |
No Summary
|
2023-06-16 |
