litex-hub
by LiteX-Hub (Organization)
by LiteX-Hub (Organization)
| Ranking | Name | Version |
|---|
To install packages from this channel, use the channel temporarily with conda or add it to your .condarc file for configured ongoing access. Learn more
| Name | Latest Version | Summary | Updated | License |
|---|
| yosys | 0.9_5477_g009940f5 | Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. | Mar 25, 2025 | ISC |
| gperftools | 2.13_20_g000af9a | — | Mar 25, 2025 | — |
| vtr-optimized | 8.0.0_6959_ga7fae8fb2 | The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. | Mar 25, 2025 | MIT |
| prjxray-db | 0.0_257_g0a0adde | Project X-Ray Database: XC7 Series. | Mar 25, 2025 | CC0-1.0 |
| prjxray-tools | 0.1_3182_g8dcc0184 | Documenting the Xilinx 7-series bit-stream format. | Mar 25, 2025 | ISC |
| surelog | 1.51_5_gdaa685050 | Parser/Compiler for SystemVerilog | Mar 25, 2025 | Apache |
| yosys-uhdm | 5028517_2022_10_03_0_g5028517 | — | Mar 25, 2025 | — |
| icestorm | 0.0_719_g792cef0 | Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. | Mar 25, 2025 | — |
| capnproto-java | 0.1.14_1_g81d1846 | Cap'n Proto in pure Java | Mar 25, 2025 | MIT |
| capnproto | 0.8.0 | An insanely fast data interchange format and capability-based RPC system. | Mar 25, 2025 | MIT |
| yosys-symbiflow-plugins | 1.20230425_62_g0ad1af2 | — | Mar 25, 2025 | — |
| prjoxide | v0.0_412_g318331f | Documenting Lattice 28nm FPGA parts | Mar 25, 2025 | ISC |
| symbiflow-yosys-plugins | 1.20230425_62_g0ad1af2 | — | Mar 25, 2025 | — |
| nextpnr-ice40 | 0.0.0_3874_g3b99db29 | nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. | Mar 25, 2025 | ISC |
| nextpnr-nexus | 0.0.0_3874_g3b99db29 | nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. | Mar 25, 2025 | ISC |
| nextpnr-fpga_interchange | 0.3_71_g06ce27ed | nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. | Mar 25, 2025 | ISC |
| nextpnr-xilinx | 0.0 | nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. | Mar 25, 2025 | ISC |
| isl | 0.21 | a thread-safe C library for manipulating sets and relations of integer points bounded by affine constraints. | Mar 25, 2025 | MIT |
| libusb | 1.0.20 | A cross-platform library to access USB devices | Mar 25, 2025 | LGPLv2.1 |
| libftdi | 1.3 | FTDI USB driver with bitbang mode | Mar 25, 2025 | LGPLv2.1 |
| binutils-riscv64-elf | 2.34 | A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. | Mar 25, 2025 | GPL |
| gcc-riscv64-elf-nostdc | 10.1.0 | The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...). | Mar 25, 2025 | GPL |
| gcc-riscv64-elf-newlib | 10.1.0 | The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...). | Mar 25, 2025 | GPL |
| openocd | 0.12.0_rc2_19_g9d925776b | OpenOCD provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support | Mar 25, 2025 | GPLv2+ |
| libunwind | 1.5.0 | — | Mar 25, 2025 | — |