prjtrellis
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
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v1.0_176_gf93243b
1.4_66_g2dab009
1.4_64_g36c615d
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1.2.1_24_g86d8e36
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About
Summary
Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
Information Last Updated
Mar 25, 2025 at 16:23
License
ISC
Total Downloads
75.6K
Platforms
Linux 64 Version: 1.2.1_24_g86d8e36
Win 64 Version: 1.0_176_gf93243b
macOS 64 Version: 1.3_9_g1495455