The fastest Verilog HDL simulator
copied from cf-staging / verilator-debugWelcome to Verilator, the fastest Verilog HDL simulator. • Accepts synthesizable Verilog or SystemVerilog • Performs lint code-quality checks • Compiles into multithreaded C++, or SystemC • Creates XML to front-end your own tools Fast • Outperforms many commercial simulators • Single- and multi-threaded output models Widely Used • Wide industry and academic deployment • Out-of-the-box support from Arm, and RISC-V vendor IP Community Driven & Openly Licensed • Guided by the CHIPS Alliance and Linux Foundation • Open, and free as in both speech and beer • More simulation for your verification budget Commercial Support Available • Commercial support contracts • Design support contracts • Enhancement contracts
