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gcc-ppc64le-linux-musl
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public |
The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...).
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2023-06-18 |
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gcc-riscv64-elf-newlib
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public |
The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...).
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2023-06-16 |
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capnproto-java
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public |
Cap'n Proto in pure Java
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2023-06-16 |
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capnproto
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public |
An insanely fast data interchange format and capability-based RPC system.
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2023-06-16 |
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wishbone-tool
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public |
All-in-one Wishbone binary, available for a variety of platforms. Useful for interacting with the internal Wishbone bridge on a device.
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2023-06-16 |
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dtc
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public |
Device Tree Compiler (dtc) toolchain for working with device tree source and binary files and also libfdt, a utility library for reading and manipulating the binary format.
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2023-06-16 |
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gcc-riscv64-elf-nostdc
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public |
The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...).
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2023-06-16 |
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binutils-riscv64-elf
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public |
A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code.
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2023-06-16 |
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openocd
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public |
OpenOCD provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support
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2023-06-16 |
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iceprog
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public |
Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
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2023-06-16 |
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libftdi
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public |
FTDI USB driver with bitbang mode
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2023-06-16 |
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dfu-util
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public |
Device Firmware Upgrade Utilities
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2023-06-16 |
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fxload
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public |
A continuation of the fxload tool from linux-hotplug.
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2023-06-16 |
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libxml2
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public |
The XML C parser and toolkit of Gnome
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2023-06-16 |
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flterm
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public |
Serial boot program for MiSoC
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2023-06-16 |
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libusb
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public |
A cross-platform library to access USB devices
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2023-06-16 |
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icefunprog
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public |
Programmer for Devantech iCE40 modules, iceFUN and iceWerx
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2023-06-16 |
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nextpnr-xilinx
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2023-06-16 |
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nextpnr-ecp5
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2023-06-16 |
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uhdm-integration-yosys
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public |
No Summary
|
2023-06-16 |
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nextpnr-ice40
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public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2023-06-16 |
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yosys-uhdm
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public |
No Summary
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2023-06-16 |
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uhdm-integration-verilator
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public |
No Summary
|
2023-06-16 |
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nextpnr-generic
|
public |
nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool.
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2023-06-16 |
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arachne-pnr
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public |
Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device. Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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2023-06-16 |
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verilator-uhdm
|
public |
No Summary
|
2023-06-16 |
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symbiflow-yosys-plugins
|
public |
No Summary
|
2023-06-16 |
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antmicro-yosys-complete
|
public |
Conda metapackage combining Antmicro Yosys fork and Yosys plugins.
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2023-06-16 |
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symbiflow-yosys
|
public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2023-06-16 |
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antmicro-yosys-plugins
|
public |
No Summary
|
2023-06-16 |
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antmicro-yosys
|
public |
No Summary
|
2023-06-16 |
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quicklogic-vtr-gui
|
public |
A metapackage installing upstream version of the Verilog-to-Routing (VTR) with GUI support.
|
2023-06-16 |
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surelog
|
public |
Parser/Compiler for SystemVerilog
|
2023-06-16 |
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surelog-uhdm
|
public |
No Summary
|
2023-06-16 |
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quicklogic-vtr
|
public |
A metapackage installing upstream version of the Verilog-to-Routing (VTR).
|
2023-06-16 |
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vtr-optimized
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
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2023-06-16 |
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sv-parser
|
public |
SystemVerilog parser library fully complient with IEEE 1800-2017
|
2023-06-16 |
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odin_ii
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public |
Odin II is used for logic synthesis and elaboration, converting a subset of the Verilog Hardware Description Language (HDL) into a BLIF netlist.
|
2023-06-16 |
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vtr-gui
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2023-06-16 |
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slang
|
public |
Parser and compiler library for SystemVerilog
|
2023-06-16 |
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moore
|
public |
HDL compiler based on LLHD
|
2023-06-16 |
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verible
|
public |
The main mission is to parse SystemVerilog (IEEE 1800-2017) for a wide variety of applications.
|
2023-06-16 |
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symbiflow-vtr-gui
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2023-06-16 |
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vtr
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2023-06-16 |
|
symbiflow-vtr
|
public |
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
|
2023-06-16 |
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yosys
|
public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2023-06-16 |
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quicklogic-yosys
|
public |
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
|
2023-06-16 |
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verilator
|
public |
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators.
|
2023-06-16 |
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xilinx-vivado
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public |
Conda metapackage for Xilinx Vivado SDK. Package checks only Vivado version.
|
2023-06-16 |
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iverilog
|
public |
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format.
|
2023-06-16 |
