antmicro
by antmicro
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Packages
| Name | Latest Version | Summary | Updated | License |
|---|
| renode | 1.12.0_506_g929116c | — | Mar 25, 2025 | The MIT License (MIT) |
| gcc-riscv64-elf-newlib | 12.1.0 | The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...). | Mar 25, 2025 | GPL |
| binutils-riscv64-elf | 2.39 | A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. | Mar 25, 2025 | GPL |
| gcc-riscv64-elf-nostdc | 12.1.0 | The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...). | Mar 25, 2025 | GPL |
| gcc-ppc64le-linux-musl | 12.1.0 | The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...). | Mar 25, 2025 | GPL |
| libxml2 | 2.9.9 | The XML C parser and toolkit of Gnome | Mar 25, 2025 | MIT |
| libusb | 1.0.20 | A cross-platform library to access USB devices | Mar 25, 2025 | LGPLv2.1 |
| iverilog | 0_8_5850_g540555fc | Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp' command. For synthesis, the compiler generates netlists in the desired format. | Mar 25, 2025 | GPLv2 |
| libftdi | 1.3 | FTDI USB driver with bitbang mode | Mar 25, 2025 | LGPLv2.1 |
| symbiflow-yosys | 0.9_0_g40d9e120 | Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. | Mar 25, 2025 | ISC |
| capnproto | 0.8.0 | An insanely fast data interchange format and capability-based RPC system. | Mar 25, 2025 | MIT |
| xilinx-vivado | 2020.1 | Conda metapackage for Xilinx Vivado SDK. Package checks only Vivado version. | Mar 25, 2025 | — |
| capnproto-java | 0.1.5_18_gcf62cd4 | Cap'n Proto in pure Java | Mar 25, 2025 | MIT |
| quicklogic-yosys | 0.8.0_93_gb2a09da0 | Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. | Mar 25, 2025 | ISC |
| binutils-riscv32-elf | 2.34 | A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. | Mar 25, 2025 | GPL |
| binutils-or1k-elf | 2.34 | A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. | Mar 25, 2025 | GPL |
| binutils-sh-elf | 2.34 | A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. | Mar 25, 2025 | GPL |
| binutils-lm32-elf | 2.34 | A set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. | Mar 25, 2025 | GPL |
| icestorm | 0.0_719_g792cef0 | Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. | Mar 25, 2025 | — |
| openocd | 0.11.0_396_ga0bd3c992 | OpenOCD provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support | Mar 25, 2025 | GPLv2+ |
| prjtrellis | 1.0_176_gf93243b | Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation. | Mar 25, 2025 | ISC |
| vtr-gui | 8.0.0_3352_g8dcd60cce | The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. | Mar 25, 2025 | MIT |
| vtr | 8.0.0_3352_g8dcd60cce | The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. | Mar 25, 2025 | MIT |
| iceprog | 0.0_719_g792cef0 | Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. | Mar 25, 2025 | — |
| antmicro-yosys | v0.0_156_gde7835a | — | Mar 25, 2025 | — |