Project Trellis enables a fully open-source flow for ECP5 FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Trellis itself provides the device database and tools for bitstream creation.
| Label | Latest Version |
|---|---|
| main | 1.0_176_gf93243b |
| ci-master-1164514854 | 1.0_176_gf93243b |
