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Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Label Latest Version
main 0.8_0326_g807b3c76
ci-master-939595724 0.9_5457_gc6681508
ci-master-1188059080 0.9_5586_gb2e97174
ci-master-1613391290 0.12_43_g7407a7f3e
ci-master-1925127487 0.14_67_g3818e1160
ci-master-2229869394 0.16_59_gb30d90a14

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