yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Installation
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About
Summary
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Last Updated
Jul 11, 2021 at 23:19
License
ISC
Total Downloads
3.6M
Supported Platforms
linux-64
Unsupported Platforms
win-64 Last supported version: 0.9_4635_ga9b61080
macOS-64 Last supported version: 0.27_34_ga2655a4b7