Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.
| Label | Latest Version |
|---|---|
| main | 1.5.119_74_g7e42483 |
| ci-HEAD-2390665516 | 1.5.221_0_g661c9ee |
| ci-master-2471692226 | 1.5.222_0_g4a7b6bf |
| ci-master-2525626987 | 1.5.224_0_gd3407b3 |
